Insights from Evaluating the FlatBuffers Workload on Andes RISC-V
Mia Chang, Andes Technology
Summary
The memory wall is no longer a theoretical concern. It is the defining bottleneck in today’s AI, automotive, and data center SoCs. CPUs operate at GHz frequencies with single-digit nanosecond cycle times, yet DRAM latency remains stubbornly at 60 ─ 100 ns, and MMIO accesses to on-chip accelerators across complex Networks-on-Chip can take even longer. As SoC designs scale up with more accelerators, larger memory subsystems, and deeper interconnect fabrics, the cost of every cache miss and every device register access grows. No single architectural feature can solve this. It demands a multi-dimensional approach.
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core. Our evaluation confirmed that outstanding transaction capability delivers significant benefit, up to 39%, when memory accesses are independent, but only 6% under pointer-chasing patterns where hard data dependencies prevent parallelism. This demonstrates exactly why a single-dimensional solution is insufficient. The Andes AX46MPV addresses memory latency from multiple angles: outstanding transactions to exploit memory-level parallelism when access patterns allow, hardware prefetching to predict and fetch data before the core needs it, and software prefetch support to give programmers direct control over latency hiding. Together, these capabilities form a comprehensive latency tolerance strategy — ensuring robust CPU performance whether the bottleneck is cacheable DRAM access or uncacheable MMIO traffic across the SoC.
The full article will be available soon. Stay tuned!
