Silicon Valley, USA
DoubleTree By Hilton San Jose
2050 Gateway Place, San Jose, CA, 95110, US
Both Days Are Free To Attend.
Deep Dive
April 20, 2026
Available as an add-on when registering. Limited Seating. A $30 deposit is required to reserve a spot & will be refunded when you attend.
Main Conference
April 21, 2026
Free to Attend
AGENDA
| Start | End | Session | Speaker |
|---|---|---|---|
| 8:00 AM | 9:15 AM | Breakfast & Registration | |
| 9:15 AM | 9:35 AM | Your RISC-V Now! | Frankwell Lin, Andes Technology |
| 9:35 AM | 10:00 AM | How AI Really Works | Linley Gwennap, Author |
| 10:00 AM | 10:25 AM | Solving Low-latency, Efficient Inferencing in the Datacenter | Satyam Srivastava, d-Matrix |
| 10:25 AM | 10:40 AM | Evolving AI Data Center Architectures for Densification and High-Radix Connectivity | Saurabh Gayen, Baya Systems |
| 10:40 AM | 11:10 AM | Coffee Break | |
| 11:10 AM | 11:35 AM | Building an AI Inference Platform on RISC-V | Koby Soden, Axelera |
| 11: 35 AM | 12:00 PM | RISC-V: Spanning Datacenter to Edge | Oliver Jones, AION Silicon |
| 12:00 PM | 12:30 PM | Innovating Next-Generation SoCs with the Latest Andes RISC-V Solutions Now! | Charlie Su, Andes Technology |
| 12:30 PM | 1:45 PM | Lunch | |
| 1:45 PM | 2:00 PM | Solving RISC-V Sub-System Verification: AIA, IOMMU and Other Flash Points | Adnan Hamid, Breker |
| 2:00 PM | 2:25 PM | From the Lab to the Car | Pedro Lopez, Quintauris |
| 2:25 PM | 2:40 PM | Connecting and securing RISC-V designs with Arteris | Guillaume Boillet, Arteris |
| 2:40 PM | 3:05 PM | ASIL Safety: More Than DCLS | Darren Jones, Andes Technology |
| 3:05 PM | 3:35 PM | Coffee Break | |
| 3:35 PM | 4:20 PM | Expert Panel: Deploying RISC-V in High-Performance Systems | Amber Huffman, Google Steve Wanless, RedHat Jeffrey Law, Qualcomm Moderator: Marc Evans, Andes Technology |
| 4:20 PM | 4:40 PM | RISC-V Tailwinds are Stronger than Ever | Marc Evans, Andes Technology |
| 4:40 PM | 6:00 PM | Evening Reception |
EXPERT PANEL
Deploying RISC-V in High-Performance Systems
Amber Huffman
Principal Engineer
Steve Wanless
RHEL Business Strategist for Infrastructure Components
Jeffrey Law
Sr. Director, Engineering
SPEAKERS
Oliver Jones
CEO
RISC-V: Spanning Datacenter to Edge
Linley Gwennap
Technology Analyst & Author
How AI Really Works
Koby Soden
Solutions Architect
Building an AI Inference Platform on RISC-V
Satyam Srivastava
Distinguished Architect
Solving Low-latency, Efficient Inferencing in the Datacenter
Pedro Lopez
Marketing Strategy Officer
From The Lab to The Car
Guillaume Boillet
VP of Strategic Marketing
Connecting & Securing RISC-V Designs with Arteris
Saurabh Gayen
Chief Solutions Architect
Evolving AI Data Center Architectures for Densification & High-Radix Connectivity
Adnan Hamid
CTO
Solving RISC-V Sub-System Verification: AIA, IOMMU and Other Flash Points
Dr. Charlie Su
CTO & President
Darren Jones
Distinguished Solutions Architect
ASIL Safety: More Than DCLS
Frankwell Lin
Chairman & CEO
Marc Evans
Director of Business Development & Marketing
DEEP DIVE DAY
There will be four one-hour hands on technical sessions on the following topics:
Trevor Cooper
System Architecture
Unlocking RISC-V AI Performance with RVP and RVV
This hands-on workshop demonstrates how AI inference performance scales using packed-SIMD (RVP), and vector (RVV) implementations. Using a standardized benchmark, attendees will perform hands-on measurements and gain insight into performance scaling and software optimization strategies for next-generation RISC-V AI platforms.
Mia Chang
FAE Manager
Beyond the Benchmark: Accelerating Exponential Functions for High-Performance Vector Units
Learn to eliminate “invisible” bottlenecks in RISC-V. This technical deep dive showcases an exponential algorithm optimized via utilizing SystemC modeling and pipeline analysis to ensure your AI activation functions hit peak throughput with precision.
Joseph Tsai
FAE Manager
Accelerate Hotspots with Custom Instructions
Many workloads spend significant time on a small set of critical operations. This session explores a methodology to identify hotspots and develop RISC-V custom hardware, reducing both instruction count and execution cycles – demonstrating how custom instructions can unlock substantial performance gains for specialized workloads.
Saurabh Gayen
Chief Solutions Architect
High-Radix AI Switch Design Using NeuraScale: Scaling beyond Crossbars
As AI data center systems scale, switch architectures must support rapidly increasing bandwidth and radix. Traditional crossbars are struggling to scale to these extreme levels, while mesh-based NoCs (Network-on-Chip) fail to provide the non-blocking performance required for AI workloads. In this session, we present NeuraScale Fabric IP, a novel on-die NoC that leading switch vendors are adopting to build extremely high-radix AI switches. Through a live demo, we show how Baya Systems’ FabricStudio software enables the design and scaling of NeuraScale fabrics to support very high port counts while delivering non-blocking performance without fabric hotspots.
REGISTRATION
PARTNERS
