Silicon Valley, USA
DoubleTree By Hilton San Jose
2050 Gateway Place, San Jose, CA, 95110, US
Both Days Are Free To Attend.
Deep Dive
April 20, 2026
Available as an add-on when registering. Limited Seating. A $30 deposit is required to reserve a spot & will be refunded when you attend.
Main Conference
April 21, 2026
Free to Attend
BLOG
Accelerating AI with RISC-V ISA: Lessons from Hands-On DGEMM Benchmarking
In this article we share practical lessons from hands-on experiments implementing a DGEMM kernel on an Andes AX46MPV near cycle-accurate RISC-V simulator. A cycle-accurate simulator lets us observe performance at the granularity of individual processor cycles and instrument the code with hardware performance monitoring (HPM) counters to track cycle counts, instruction throughput, and memory activity — all without silicon.
Hitting the Memory Wall: Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core. Our evaluation confirmed that outstanding transaction capability delivers significant benefit, up to 39%, when memory accesses are independent, but only 6% under pointer-chasing patterns where hard data dependencies prevent parallelism.
AndeSentry – Andes’ Security Platform
Security has become a critical requirement across a wide range of applications, including mobile devices, automotive infotainment systems, and embedded platforms such as robotics. These systems must deliver robust security functionality with minimal performance overhead, which in turn requires tight and seamless integration between hardware and software to achieve optimal efficiency.
AGENDA
Download RISC-V Now! Slides
Click the button below to receive the presentation slides and video playlist from RISC-V Now! by Andes.
EXPERT PANEL
Deploying RISC-V in High-Performance Systems
Amber Huffman
Principal Engineer
Steve Wanless
RHEL Business Strategist for Infrastructure Components
Jeffrey Law
Sr. Director, Engineering
SPEAKERS
Oliver Jones
CEO
RISC-V: Spanning Datacenter to Edge
Linley Gwennap
Technology Analyst & Author
How AI Really Works
Koby Soden
Solutions Architect
Building an AI Inference Platform on RISC-V
Satyam Srivastava
Distinguished Architect
Solving Low-latency, Efficient Inferencing in the Datacenter
Pedro Lopez
Marketing Strategy Officer
From The Lab to The Car
Guillaume Boillet
VP of Strategic Marketing
Connecting & Securing RISC-V Designs with Arteris
Saurabh Gayen
Chief Solutions Architect
Evolving AI Data Center Architectures for Densification & High-Radix Connectivity
Adnan Hamid
CTO
Solving RISC-V Sub-System Verification: AIA, IOMMU and Other Flash Points
Dr. Charlie Su
CTO & President
Innovating Next-Generation SoCs with the Latest Andes RISC-V Solutions Now!
Darren Jones
Distinguished Solutions Architect
ASIL Safety: More Than DCLS
Frankwell Lin
Chairman & CEO
Your RISC-V Now!
Marc Evans
Director of Business Development & Marketing
RISC-V Tailwinds are Stronger than Ever
DEEP DIVE DAY
There will be four one-hour hands on technical sessions on the following topics:
Trevor Cooper
System Architecture
Unlocking RISC-V AI Performance with RVP and RVV
This hands-on workshop demonstrates how AI inference performance scales using packed-SIMD (RVP), and vector (RVV) implementations. Using a standardized benchmark, attendees will perform hands-on measurements and gain insight into performance scaling and software optimization strategies for next-generation RISC-V AI platforms.
Mia Chang
FAE Manager
Beyond the Benchmark: Accelerating Exponential Functions for High-Performance Vector Units
Learn to eliminate “invisible” bottlenecks in RISC-V. This technical deep dive showcases an exponential algorithm optimized via utilizing SystemC modeling and pipeline analysis to ensure your AI activation functions hit peak throughput with precision.
Joseph Tsai
FAE Manager
Accelerate Hotspots with Custom Instructions
Many workloads spend significant time on a small set of critical operations. This session explores a methodology to identify hotspots and develop RISC-V custom hardware, reducing both instruction count and execution cycles – demonstrating how custom instructions can unlock substantial performance gains for specialized workloads.
Saurabh Gayen
Chief Solutions Architect
High-Radix AI Switch Design Using NeuraScale: Scaling beyond Crossbars
As AI data center systems scale, switch architectures must support rapidly increasing bandwidth and radix. Traditional crossbars are struggling to scale to these extreme levels, while mesh-based NoCs (Network-on-Chip) fail to provide the non-blocking performance required for AI workloads. In this session, we present NeuraScale Fabric IP, a novel on-die NoC that leading switch vendors are adopting to build extremely high-radix AI switches. Through a live demo, we show how Baya Systems’ FabricStudio software enables the design and scaling of NeuraScale fabrics to support very high port counts while delivering non-blocking performance without fabric hotspots.
PARTNERS
